A conventional hardware implementation of a non-reconfigurable Bose, Ray-Chaudhuri, Hocquenghem (i.e., BCH) encoder or a Reed-Solomon (i.e., RS) encoder has a start signal that tells the encoder when a new data word is ready to be encoded. Most implementations of BCH/RS encoders do not allow changes to the parameters of the BCH/RS code, such as a maximum error limit. However, modern applications of BCH/RS codes in solid state disk flash controllers are specified to change some parameters at runtime. To achieve a fast speed, a reconfiguration time of the reconfigurable controllers should be as short as possible. Hence, the reconfigurable encoders often have a configuration interface that sets the encoder into a current configuration. The configuration interface can set the maximal error limit or the number of parity bits inserted into the codes.
A typical BCH/RS encoder is conventionally implemented using a linear feedback shift register (i.e., LFSR). If the maximum error limit “T” is fixed, the coefficients of the LFSR are constants. Thus, constant multipliers are used to implement the LFSR instead of ordinary multipliers in a Galois Field (i.e., GF). The area of a constant GF-multiplier is less than the area of non-constant GF-multiplier.
Reconfigurable BCH/RS encoders can produce different numbers of parity symbols depending on the maximum error limit T. Therefore, the coefficients of the LFSR depend on the maximum error limit T and are not constants. As such, non-constant GF multipliers are commonly implemented and so significantly increase the area of the encoder.
An existing scheme that works around the non-constant multipliers uses a reconfigurable encoder as a wrapper around a non-reconfigurable encoder. For relatively small Galois Fields, the wrapper approach has an area approximately twice as large as the non-reconfigurable designs. However, the wrapper approach still suffers from the use of some non-constant multipliers and even Galois Field inversion, which can be difficult to implement with large Galois Fields. Furthermore, the wrapper encoder also is not reconfigurable on-the-fly.
In the case of binary BCH encoders, a standard implementation of a non-reconfigurable encoder performs multiplication by a constant binary matrix in GF(2). The implementation is relatively simple and area efficient (i.e., the designs only have trees of XOR gates). To implement a reconfigurable binary BCH encoder using the same scheme, the coefficients of matrixes heavily depend on the configuration data and are not easy to calculate.
It would be desirable to implement a variable parity encoder.